Prof. Andrew Maynard

Professor of Advanced Technology Transitions, School for the Future of Innovation in Society,

Arizona State University

A New Science of Navigating Advanced Technology Transitions


The past ten thousand years and more of human history have been driven by our individual and collective ability to imagine futures that are different from the past, and to find ways of translating these into reality. It’s this ability that is at the heart of human ingenuity, our aptitude for innovation, our capacity for creative problem-solving, and our resourcefulness in inventing and leveraging increasingly advanced technologies – so much so that our collective identity and trajectory as a species can only be truly understood through the complex relationship between people, technology, and the future. This is a relationship that has evolved over time, and is one that has generally enabled individuals and communities to find innovative solutions to challenges faster than those innovations have led to new generations of problems. Yet the accelerating pace of innovation within today’s increasingly interconnected world is calling into question whether old ways of thinking about technology and society are sufficient to successfully navigate coming technology transitions, whether these are being driven by artificial intelligence, gene editing, robotics, quantum computing, or a long list of other emerging and converging technologies. Rather, there are growing indications that we need a new science of advanced technology transitions if we are to continue to flourish as a species on a healthy planet. This keynote will address the growing challenges of ensuring human flourishing on a healthy planet in an era of increasingly transformative advanced technology transitions, and will explore emerging opportunities for helping guide new technological capabilities in directions that benefit rather than hinder positive futures.


Professor Andrew Maynard is a scientist, author, thought leader, and Professor of Advanced Technology Transitions in the ASU School for the Future if Innovation in Society. He is the founder of the ASU Future of Being Human initiative, Director of the ASU Risk Innovation Nexus, and was previously Associate Dean in the ASU College of Global Futures. His work focuses on successfully transitioning to a future where transformative technologies from artificial intelligence and quantum computing to gene editing, nanotechnology, automation, and more, have the power to fundamentally change every aspect of society. He writes about emerging technologies and responsible innovation on The Future of Being Human Substack.

Professor Maynard is an elected Fellow of the American Association for the Advancement of Science, serves as co-chair of the Institute for the Advancement of Nutrition and Food Science (IAFNS) Board of Trustees, is a member of the Canadian Institute for Advanced Research President’s Advisory Committee, has served on a number of National Academies of Sciences committees, and has testified before congressional committees on several occasions. Since 2008 he has worked closely with the World Economic Forum in a number of capacities, including chairing and serving on various Global Agenda Councils/Global Future Councils, and contributing to the WEF/Scientific American annual list of Top Ten Emerging Technologies.

Prof. Hyuk-Jae Lee

Architecture and Parallel Processing Lab,

Seoul National University

Recent advancement in Processor-Memory Architecture for Large AI Models


Recent advancements in generative AI have significantly drawn attention due to their rapid technological progress. In managing large-scale deep learning models, the extensive data transfer between processors and memory leads to slow computing speed and substantial power consumption. Consequently, to enhance computing speed and reduce the power consumption associated with data transfer, it is crucial to minimize the distance between computing units and memory devices. To achieve this objective, recent developments in Processing-in-Memory (PIM) and Processing-near Memory (PNM) technologies have emerged. In this presentation, I will provide an overview of the evolution of PIM and PNM technologies. One of the most widely used approaches in implementing PIM involves incorporating the computation units separately from the storage cells within the DRAM itself. This approach ensures that computational operations are closely integrated with memory storage while maintaining a distinct separation from the actual storage cells, thereby minimizing alterations to the structure of the storage cells.

Additionally, an interconnect standard like Compute Express Link (CXL) supports the implementation of computational units in close proximity to memory devices. While CXL is useful for expanding memory capacity, the host processor may suffer from slow access speed to the memory expanded by CXL. However, operating processing units close to CXL memory, a technique known as PNM, can be an effective approach for improving performance and reducing power consumption. In this talk, I will delve into diverse processor-memory architectures and shed light on the latest research trends aimed at effectively harnessing their potential.


Hyuk-Jae Lee earned his B.S. M.S. degrees in electronics engineering from Seoul National University in 1987 1989, respectively. Subsequently, he pursued a Ph.D. degree in electrical computer engineering at Purdue University in West Lafayette, IN, USA, successfully completing it in 1996.

From 1996 to 1998, he served on the faculty of the Department of Computer Science at Louisiana Tech University in Ruston, LS, USA. Following this, from 1998 to 2001, he held the position of Senior Component Design Engineer with the Server Workstation Chipset Division at Intel Corporation in Hillsboro, OR, USA.

In 2001, Dr. Lee joined the School of Electrical Computer Engineering at Seoul National University, where he currently holds the position of Professor. Additionally, he founded Mamurian Design, Inc., Seoul, a fabless SoC design house specializing in multimedia applications.

Dr. Lee also served as the President of IEIE (The Institute of Electronics Information Engineer) in Korea. His research interests primarily center on computer architecture SoC (System-on-Chip) design tailored for AI (Artificial Intelligence) applications.

Prof. Jing-Ming Guo

Director of Advanced Intelligent Image and Vision Technology Research Center,

National Taiwan University of Science and Technology

Development Trends and Considerations for Practical Applications of Generative AI


This presentation explores the latest trends in Generative AI, focusing on key topics such as the evolution of GPT, expert-level optimization in large language models (LLMs), micro-sizing LLMs, and the deployment of Generative AI in Taiwan’s Industrial Technology Research Institute (ITRI) and its potential expansion to Taiwanese enterprises. The talk delves into the advancements in GPT models, highlights the significance of expert-level optimization techniques in enhancing LLM performance, and discusses strategies for scaling down large models. Moreover, it showcases the current efforts by ITRI in implementing Generative AI and outlines the future prospects of adopting this technology within Taiwan’s business landscape.


Prof. Guo received the Ph.D. degree from the Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, in 2004. He is currently a full Professor with the Department of Electrical Engineering, and Director of Advanced Intelligent Image and Vision Technology Research Center. He was Vice Dean of the College of Electrical Engineering and Computer Science, and Director of the Innovative Business Incubation Center, Office of Research and Development. He was Visiting Scholar at the Digital Video and Multimedia Lab, Department of Electrical Engineering, Columbia University, USA from June to August, 2015, and the Signal Processing Lab, Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA from July 2002 to June 2003 and June-November, 2014. His research interests include multimedia signal processing, biometrics, computer vision, and digital halftoning.

Dr. Guo is a Senior Member of the IEEE and Fellow of the IET. He has been promoted as a Distinguished Professor in 2012 for his significant research contributions. He has received many awards, including Best Paper Awards (IEEE ICCE-TW 2020, IS3C 2020, NSSSE 2020, ICSSE 2011 and 2020, ICS 2014, and CVGIP 2005, 2006, 2013, 2016, and 2019), Outstanding Contribution Award from Taiwan Consumer Electronics Society in 2021, Outstanding Electrical Engineering Professor Award from Chinese Institute of Electrical Engineering, Taiwan in 2016, Outstanding Research Contribution Award from Institute of System Engineering in 2017, Excellence Research Awards from his university for five times (2008, 2011, 2014, 2017, 2020, and 2022, this award is evaluated and issued every three years), Outstanding Industry-Academia Collaboration Awards from Ministry of Science and Technology, Taiwan, in 2013. Outstanding youth Electrical Engineer Award from Chinese Institute of Electrical Engineering in 2011, Outstanding young Investigator Award from Taiwan Institute of System Engineering in 2011.

Prof. Shoji Kasahara

Division of Information Science, Graduate School of Science and Technology,

Nara Institute of Science and Technology

Performance Modeling of Bitcoin Blockchain –
How is the Transaction –
Confirmation Time Affected by Transaction Fee?


In Bitcoin system, transactions are prioritized according to transaction fees. Transactions without fees are given low priority and likely to wait for confirmation. It is important to quantitatively investigate how transactions with small fees of Bitcoin affect the transaction- confirmation time.

In this talk, we first introduce the Bitcoin system, focusing on proof-of-work (PoW), the consensus mechanism of Bitcoin blockchain. Then, we show two stochastic models of Bitcoin blockchain; a priority queueing model with batch service, and the classical urn model without replacement. The former models the transaction-confirmation process, while the latter captures the PoW-based mining mechanism. With these models, we analyze the transaction confirmation time, discussing how the fee of a transaction affects the transaction-confirmation time.


Shoji Kasahara was born in Hamamatsu City, Shizuoka Pref., Japan, in 1965. He received the B. Eng. degree from the Department of Applied Mathematics and Physics, Faculty of Engineering, Kyoto University, Kyoto, Japan, in 1989. He received the M. Eng. and Dr. Eng. degrees from the Division of Applied Systems Science, Faculty of Engineering, Kyoto University, in 1991 and 1996, respectively. He was with the Educational Center for Information Processing at Kyoto University from 1993 to 1997 as an Assistant Professor.

In 1996, he was a visiting scholar at the University of North Carolina at Chapel Hill, NC, USA. He was also a visiting scholar at the University of Waterloo, Canada, in July 1996. From 1997 to 2005, he was with the Department of Information Systems, Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan. From 2005 to 2012, he was an Associate Professor of the Department of Systems Science, Graduate School of Informatics, Kyoto University, Kyoto, Japan. Since 2012, he has been a Professor of Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma, Nara, Japan. His research interests include queueing theory and performance analysis of computer and communication systems. He is a fellow of IEICE and ORSJ, a senior member of IEEE, and a member of INFORMS, IPSJ, and ISCIE.